SI Webinar Series from Samtec
Are you ready to unlock the secrets of signal integrity and take your knowledge to the next level? Look no further. If you are an aspiring engineer, a seasoned professional, or simply a tech enthusiast, understanding the intricacies of signal integrity is challenging. Samtec’s SI experts are ready to help answer the fundamentals on Signal Integrity, right at your fingertips during these live webinar talks.
Latest Webinar | Upcoming Webinars | On Demand Webinars | More Information
Latest Webinar
March 21, 2024
Advantages and Limitations of Generalized Open-Pin-Field Modeling For Array Connectors
Watch Video | Download PPT
A study of how to model open-pin-field array connectors with a focus on cumulative modeling errors, bandwidth considerations, passivity and crosstalk.
Upcoming Webinars
*Schedule is subject to change at anytime.
April 18, 2024
3 Design Tips for Power Distribution Networks
2:15 PM (EST)
Presenter: Istvan Novak
Register
May 16, 2024
*Realistic use cases for edge, angled and vertical launch connectors up to 100 GHz
2:15 PM (EST)
Presenters: Gustavo Blando and Sandeep Sankararaman
Register
July 18, 2024
AWARDED BEST PAPER AT DESIGNCON 2024
Are 1.0 mm Precision RF Connectors Really Required for 224 Gbps-PAM4 Verification?
2:15 PM (EST)
Presenters: Brandon Gore
Register
On-Demand Webinars
Power Integrity
March 16, 2023
How to Measure Low PDN Impedance
Watch Video | Download PPT
Speaker: Istvan Novak
Power distribution network impedance of today’s current-hungry circuits can be in the milliohm or sub-milliohm range. Measuring such low resistances have had readily available instrumentation for decades, but measuring such low AC impedance poses multiple practical challenges. This talk will look at the challenges and list possible solutions together with practical illustrations and measurement data.
February 16, 2023
SI/PI AM(A)A – A Conversation with Scott McMorrow
Watch Video
Speakers: Matt Burns and Scott McMorrow
Scott McMorrow sets the standard as an “SI problem solver” for Samtec and its partners and customers. Please join him and Matt Burns as they reflect on key (and sometimes misunderstood) concepts that engineers working in signal integrity need to know. They will also consider trends, interesting ideas, and products recently seen at DesignCon 2023; answer audience technical questions; and share places to find good SI and PI resources.
January 19, 2023
High-Speed SI and PI – DesignCon 2023 Preview
Watch Video | Download PPT
Several Samtec team members are participating in technical sessions or panels at DesignCon 2023, which is occurring 31 January – 2 February in Santa Clara, CA. Join them in this gEEk spEEk session as they preview their research and insights, as well as answer your questions on topics such as 224 Gbps receiver design, simulation models, PCIe 6.0, PAM4, PDN measurements, and power integrity simulation. Scott McMorrow will lead the discussion as we hear from Robert Branson, Rich Mellitz (DesignCon Engineer of the Year 2022), Steve Krooswyk, and Istvan Novak (DesignCon Engineer of the Year 2020) about what they plan to present at DesignCon.
December 16, 2023
Pros and Cons of Thin Laminates in Power Distribution
Watch Video | Download PPT
Presented by: Istvan Novak
PCB laminates with dielectrics thinner than 0.1mm have been available for a couple of decades. Their primary use have been in packages and flex circuits, but power distribution in large rigid boards can also use them. We will look at the electrical properties of thin laminates and go through the pros and cons when they are used for power distribution. Simulation and measured data on test boards and production boards will complete the talk.
November 18, 2021
PDN: Loss May Be Your Friend, But Inductance is Your Enemy
Watch Video | Download PPT
Presented by: Istvan Novak
For high-speed signaling, high-frequency loss is usually considered a bad side effect that we want to minimize. The DC loss, on the other hand, matters less, because in many high-speed signaling schemes we intentionally block the DC content. In power integrity it is almost the opposite: to deliver DC power, we want to minimize the DC losses, but at the same time we don’t want high-frequency noise to travel along the power distribution network. Therefore, AC losses in power distribution are usually helpful. Inductance is different though: while it is present in all conductive structures where current flows or could flow, in power integrity the only situation when we can consider it helpful, is when the inductance is in the series path as part of an intentional low pass filtering so that we can block the noise. In applications where we don’t need the power filtering, increased inductance comes with the downside that we need more capacitance to balance it.
August 19, 2021
How to Read the ESR Curve of Capacitors
Watch Video | Download PPT
Presented by: Istvan Novak
The most widely used power distribution component is undoubtedly the bypass capacitor. After the nominal capacitance, its next most important parameter is its Effective Series Resistance, or ESR. To use bypass capacitors properly, we need to understand what exactly ESR means and how to read the ESR curve in measured or simulated plots. You will learn typical values and representative ESR curve shapes of different capacitor types.
January 21, 2021
S & Z Parameters for PDN
Watch Video | Download PPT
Presented by: Istvan Novak
In signal integrity, describing passive devices and channels with S parameters has become the norm. Power distribution is different. Dependent on the application, other forms may be best for the purpose. First we will focus on the scattering parameters of bypass capacitors. We will explain with measured and simulated data, how to use the Touchstone models that are created for series or parallel connected capacitors. Next, we will learn why design is usually done with impedances, while measurements are still done with S parameters.
December 3, 2020
Using Ferrites and Inductors in PDNs
Watch Video | Download PPT
Presented by: Istvan Novak
Do You Really Need That Ferrite Bead in Your PDN? There are two distinctly different camps of designers: people in the first camp will categorically denounce the use of ferrite beads in power distribution networks (PDN), while people in the second camp will insist that the PDN they came up with really needs the ferrite beads. This webinar will walk you through the truth about both approaches and will show, with examples, under what circumstances is it a good idea (or not) to use ferrite beads.
July 16, 2020
Multi-Layer Capacitor (MLCC) Losses
Watch Video | Download PPT
Presented by: Istvan Novak
In power distribution networks (PDN), capacitors are used in the largest number. Real-life capacitors always have parasitic resistance and inductance and those values are not guaranteed by the vendors, but capacitance is a guaranteed parameter. Surprisingly, however, many modern high-density ceramic multi-layer capacitor (MLCC) may have a huge loss of their capacitance values. In this talk we look at the reasons, consequences and potential remedies.
June 4, 2020
DC Blocking Capacitor Location
Watch Video | Download PPT
Presented by: Gustavo Blando
Have you ever wondered If it’s better to put the DC blocking capacitor close to the driver or close to the receiver? Why? A lot of confusion and friendships have been broken due to this very argument. In this talk, I’ll go back to basics and with the help of simple simulations and theory, I’ll answer those questions. Gustavo Blando is a Senior Principal Signal Integrity Architect at Samtec, Inc. In addition to his leadership roles, he’s charged with the development of new Signal Integrity/Power Integrity methodologies along with high-speed characterization, tools and modeling. Gustavo has over twenty-five years of practical experience in Signal Integrity and high-speed circuits design and has participated in numerous conference publications
May 14, 2020
The Perils of Right-Angle Turns at DC
Watch Video | Download PPT
Presented by: Istvan Novak
We all know that sharp corners and right-angle bends are not a good idea for very high-speed signaling, but what happens if we go to the other extreme of the spectrum, to DC? You may be surprised, but right-angle turns harm the DC distribution equally bad, if not more, as they harm high-speed signals. In this gEEK® spEEK Zoom webinar, we will show you why and how, and we will also show simple remedies. Istvan Novak, PhD, Life Fellow of IEEE, is a Principal Signal and Power Integrity Engineer at Samtec, working on advanced signal and power integrity designs. Prior to 2018, he was a Distinguished Engineer at SUN Microsystems, later Oracle. He worked on new technology development, power distribution and signal integrity design and validation methodologies for SUN’s successful workgroup server families. He introduced the industry’s first 25um power-ground laminates for large rigid computer boards and worked with component vendors to create a series of low-inductance and controlled-ESR bypass capacitors. Istvan has twenty-five patents to his name, author of two books on power integrity, teaches signal and power integrity courses, and maintains a popular SI/PI website.
Signal Integrity
January 18, 2024
DesignCon 2024 Preview
Watch Video | Download PPT
Presented by: Scott McMorrow, Robert Branson, Richard Mellitz, Steve Krooswyk, Brandon Gore, Sandeep Sankararaman, Istvan Novak
Samtec team leaders are presenting technical sessions and panel discussions at DesignCon 2024, which is occurring January 30th – February 1st in Santa Clara, CA. Join them in this gEEk spEEk session as they preview their research and insights as well as answer your questions on topics such as 224 Gbps receiver design, simulation models and methodologies, PCI Express, PAM4, PDN measurements, and power integrity simulation.
November 16, 2023
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures
Watch Video | Download PPT
Presenters: Matt Burns & Kiana Montes
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures Integrated RF SoCs are revolutionizing system architectures. Traditional RF interconnects strain form factor, weight and financial budgets as RF channel counts increase. In this webinar, Samtec technical experts will detail novel solutions for routing high-frequency RF signals via array connectors. Additionally, recommended launch optimizations and PCB stack-ups will be presented.
October 19, 2023
Staying Grounded in the Real World (Return Path Imperfections)
Watch Video | Download PPT
Presenter: Sandeep Sankararamen
A signal return path shares equal importance with the forward path. However, due to space constraints, physical limitations, and other parameters, designers often face challenges designing a clean return path. In this webinar, we explore sources of imperfection and offer proven design practices to optimize the return path in 112 Gbps PAM4 systems and beyond.
September 21, 2023
How to Bring S-Parameters into your Simulation Tool
Watch Video | Download PPT
Presented by: Tedd Wang
Using interconnect simulations as part of your system design allows you to see the effects of mechanical characteristics on electrical performance. But which tool should you use? And, once you have selected a toolset, what is the best way to tune your model into your channel. Join modeling experts from Samtec’s Signal Integrity Group as they address frequently asked questions and talk through common modeling sticking points, by showing detailed examples of how to quickly use the S-parameter model for the connector and the channel evaluation in ADS tool.
July 20, 2023
Breakout Design: Cable Connectors
Watch Video | Download PPT
Presenter: Scott McMorrow
Continuing the discussion from last month, Scott McMorrow provides a preview of advanced design methodology that is under development at Samtec, specifically the Samtec breakout region (BOR) methodology will be used on an NVAC near package cable (NPC) connector. Advanced BOR design methodology condenses the “final inch” of a design into a manageable region, and it was developed to addresses the complexity of designing breakouts for connectors at high data rate. Come see what the state of the art looks like and bring your questions.
June 15, 2023
Breakout Design: Package and Traces
Watch Video | Download PPT
Presenter: Scott McMorrow
Scott McMorrow explains the technical challenges of breakout region (BOR) design for packages and traces, noting how they can dramatically affect the performance of a channel. He will walk through a specific example, providing guidance on the design of the package side of a near package cable (NPC) BOR that includes 1mm pitch balls on a 30-layer board for 112Gbps PAM4. Come join this technical discussion on “final inch” design and bring your questions.
May 18, 2023
SerDes Common Mode Noise: How Much is Too Much?
Watch Video | Download PPT
Speakers: Rich Mellitz and Istvan Novak
How much common-mode noise is too much? Join Rich Mellitz and Istvan Novak as they wrestle with this question. This gEEk spEEk discussion covers why we should be concerned with common mode noise over wide frequency ranges, with a special focus on how power distribution and signaling networks impact receiver performance. What can board/system designers do to mitigate this noise? How can it be tested, measured, and modeled? Join this session to learn how you can perform simulations and measurements to evaluate your design’s sensitivity to common mode noise. Topics covered include: measurement experiments, modeling, and specifications.
April 13, 2023
Signal Integrity 101: The Fundamentals of S-Parameters
Watch Video | Download PPT
Presenter: Gustavo Blando
This talk is designed for engineers who would appreciate some SI fundamentals. In this gEEk spEEk, join Gustavo Blando as he covers the fundamentals of S-parameters and puts them to work in a real-world example. Topics covered include: the history of why S-parameters are used, their advantages, and practical use cases of S-parameters. This gEEk spEEK talk will also explain renormalization impedance and how can we use it to our advantage. Bring your questions!
February 16, 2023
SI/PI AM(A)A – A Conversation with Scott McMorrow
Watch Video
Speakers: Matt Burns and Scott McMorrow
Scott McMorrow sets the standard as an “SI problem solver” for Samtec and its partners and customers. Please join him and Matt Burns as they reflect on key (and sometimes misunderstood) concepts that engineers working in signal integrity need to know. They will also consider trends, interesting ideas, and products recently seen at DesignCon 2023; answer audience technical questions; and share places to find good SI and PI resources.
January 19, 2023
High-Speed SI and PI: DesignCon 2023 Preview
Watch Video | Download PPT
Several Samtec team members are participating in technical sessions or panels at DesignCon 2023, which is occurring 31 January – 2 February in Santa Clara, CA. Join them in this gEEk spEEk session as they preview their research and insights, as well as answer your questions on topics such as 224 Gbps receiver design, simulation models, PCIe 6.0, PAM4, PDN measurements, and power integrity simulation. Scott McMorrow will lead the discussion as we hear from Robert Branson, Rich Mellitz (DesignCon Engineer of the Year 2022), Steve Krooswyk, and Istvan Novak (DesignCon Engineer of the Year 2020) about what they plan to present at DesignCon.
August 18, 2022
Cascaded or End-to-End Models: What Do We Give Up?
Watch Video | Download PPT
Presented by: Robert Branson
To combat increased simulation times, it is common practice to divide the board and multi-pin connector models into separate simulations that are then cascaded. This practice introduces impedance and crosstalk inaccuracies between simulation and measurements. This presentation demonstrates the differences through correlated simulation/measurement models. Field plots are used to show the inaccuracy created by the artificial simulation boundary. Then we study efforts to devise mitigation strategies to decrease simulation time while avoiding simulation inaccuracy, though the best solution often comes to a monolithic simulation.
April 28, 2022
Mitigating the Effects of Connector Mating/Normal Forces in SI
Watch Video | Download PPT
Presented by: Juan Aguirre
Normal forces are a critical specification in the mating of high-performance interconnects. Normal forces minimize or eliminate oxide build-up, affect contact pin deflection, and determine surface contact area. Changes in normal forces can be observed in standard SI parameters including characteristic impedance, TDR ad RL. In this course, technical experts from Samtec will discuss measurement techniques for spotting normal force discontinuities. Mitigation solutions will also be presented.
February 24, 2022
Single Ended Design Analysis in a Different World
Watch Video | Download PPT
Presented by: Chris Kocuba
Differential analysis can mask high speed design or solver issues. Analyzing single ended data can bring these issues to light and allow the designer to reclaim performance that would otherwise be lost. These issues can be found in but not limited to: connector design, BORs, trace routing, signal definition and from model solver settings.
October 14, 2021
Advanced HD BOR & Crosstalk Mitigation Strategies
Watch Video | Download PPT
Presented by: Travis Ellis
Today’s high density connector arrays face significant challenges at the board attach region. Insertion loss and return loss impairments can be mitigated with careful design and simulation. More importantly especially with PAM4 signally are the crosstalk impairments from the associated via fields. Sympathetic resonators can allow crosstalk to skip across the entire filed with minimal attenuation. This presentation will highlight these issues and demonstrate how to improve the connector & board ecosystem to assure successful system designs.
September 16, 2021
Development of 112 Gbps PAM4 Test Platforms
Watch Video | Download PPT
Presented by: Jean-Remy Bonnefoy
The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This talk will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.
July 15, 2021
Common Mode Conundrums
Watch Video | Download PPT
Presented by: Richard Mellitz
It has long been thought that common mode impairments may be easily controlled with common mode specifications. Differential simulation may indeed have some common mode included within the signal and noise transmission. The problem emerges between specification for separable interfaces such as cards, connectors, and chips. IEEE802.3 and OIF CEI standards often include a collection of common mode specifications measured at test points for these separations or interfaces. As 112 Gb/s PAM4 becomes more common place it is worth exploring common mode specifications and what they mean for performance. What matters more and what is not so important. Discussions include the nature of common mode, a historical perspective, procedures to compute the effects of CM, CM measurements, and practices to minimize the effect of common on differential signaling.
June 17, 2021
Advanced Test Fixture Design
Watch Video | Download PPT
Presented by: Travis Ellis
Engineering systems for 112G introduces complex interdependent design challenges. More now than ever system engineers are forced to utilize a closed loop design process. Where 3D full wave simulations are used to validate designs before fabrication. Once fabricated these designs and their channel models must be correlated to measured data. To have clear picture of the results test fixtures must be transparent. Achieving fixture transparency is possible with careful design practices along with a deep understanding of what it takes to create these fixtures.
May 20, 2021
Causality Enforcement
Watch Video | Download PPT
Presented by: Stefaan Sercu
The quality of time domain simulation results, using Fourier transformations (e.g. COM simulations), depends highly on the quality of the S–parameter models used. Causality is shown to be an important parameter limiting the usefulness of a model. In this webinar we show that causality problems can be classified as mathematical and physical in origin.
February 18, 2021
Bending EM Simulation Tools
Watch Video | Download PPT
Presented by: Scott McMorrow
There is an art and science to utilizing an electromagnetic modeling tool to analyze and optimize designs and obtain reasonable answers consistently. Session attendees will learn how to “trick” a tool into providing the most accurate insight possible for a design. We’ll talk about setup, ports, boundary conditions and other tricks of the trade that help derive the best results from EM Tools. We’ll also discuss quick ways to obtain approximate answers that will help engineers maximize their efficiency.
November 19, 2020
Practical Uses of ERL in BOR Design
Watch Video | Download PPT
Presented by: Scott McMorrow
In ERL Part 1, Samtec Distinguished Engineer Rich Mellitz discussed the foundations of Effective Return Loss (ERL as a metric for full link analysis. In Part 2, Samtec Strategic Technologist Scott McMorrow will discuss a practical usage of ERL in the analysis and optimization of via and connector Breakout Regions (BOR). ERL will be used as a valuable tool in the rapid and unambiguous selection of the best design for a given data rate out of multiple design iterations.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
September 24, 2020
Periodic Discontinuities
Watch Video | Download PPT
Presented by: Gustavo Blando
In this introductory talk, I’ll start by reviewing resonances commonly found in SI topologies in an intuitive way. In particular, I’ll concentrate on half wave resonances. At a very fundamental level I’ll discuss: What resonances are? How do they develop? And how to identify them with dips/peaks in the frequency domain S-parameters? The study of half wave resonances will set the baseline to understand periodical discontinuities. The theory will be presented first and then, several examples and practical mitigation strategies will be shown for both half wave resonances and periodical discontinuities.
September 10, 2020
Noise and Simulation Correlation
Watch Video | Download PPT
Presented by: Richard Mellitz
Opinions on correlation range from intuitive to scientific. The presentation opens with an introduction of statistical terms. A simple example is used to illustrate a key question, “What is the purpose of the correlation?” An example of 100 Gbs / PAM-4 signaling correlation segues into BER correlation. Methods using noise parameters in COM are then used to correlate measured BER and simulated BER.
August 27, 2020
High-Speed Connector SI Round-Up
Watch Video | Download PPT
Presented by: John Abbott
As data rates continue to rise, interconnect choices are more critical than ever. This presentation explores the inherent signal integrity trade-offs from different connectors types and options. Topics include: SI trade-offs of popular PCB attachment options like BGA, SMT & press-fit, open pin field vs dedicated ground connector designs and the challenges of edge card designs.
August 13, 2020
Trace Corner Bends: OK or Not?
Watch Video | Download PPT
Presented by: Scott McMorrow
As system data rates become progressively faster, the difficulty of designing high-margin becomes more difficult each year. There are many misconceptions about the signal integrity implications of corner bends in high performance PCB designs. In this webinar, we will perform 3D electromagnetic investigations of individual and serpentine, single-ended and differential corners, to determine layout requirements for multiple data rate regimes. Clear guidance will be provided for both production and precision measurement board designs.
July 30, 2020
Signal Power & Noise and SI
Watch Video | Download PPT
Presented by: Richard Mellitz
The purpose is to tie it together: signals, noise power, and performance. This is a primer on how signal integrity (SI) simulations work. The context is differential signaling with data rates greater than 25 Gb/s. Examples include 100 Gb/s NRZ signaling and relations to PAM. Reviews include SI assumptions such as linear time invariance (LTI), summing noise power, superposition, and statistical convolution. A variety of other impairments such as jitter, semiconductor noise, etc. will not be covered for simplicity.
July 2, 2020
IEEE Channel Operating Margin (COM)
Watch Video | Download PPT
Presented by: Brandon Gore
During the development of the Ethernet Std-802.3 for 25 Gbps NRZ signaling, a paradigm shift happened for interconnect characterization. Frequency domain masks were replaced with an open source simulation method that ties transmitter, receiver and channel together. In this webinar presentation, we explore why these new methods where introduced and take a deeper dive into the physical representation of the reference packages.
June 25, 2020
Trace Design for Crosstalk Reduction
Watch Video | Download PPT
Presented by: Scott McMorrow
Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined, and simple rules are derived that can be used to quickly aid in system design. Scott McMorrow currently serves as CTO for Samtec’s Signal Integrity Group, Inc. As a consultant for years too numerous to mention, Scott has helped many companies develop high performance products, while training signal integrity engineers. Today he works for “the man,” where he continues being a problem solver, a change agent and “betting his job” every day.
June 18, 2020
Breakout Region Design by Inspection
Watch Video | Download PPT
Presented by: Travis Ellis
What can you do to check your layout and design breakouts with your eyes. Travis Ellis is a signal integrity practitioner working with customers to successfully deliver their systems to market. He believes signal integrity is critical for success and has delivered many innovative solutions across multiple industries. Travis holds a mechanical engineering degree from Portland State University. Travis enjoys the outdoors and the opportunity to work with many talented peers.
June 11, 2020
Impedance Corrected De-Embedding
Watch Video | Download PPT
Presented by: Stefaan Sercu
To perform accurate measurements of devices, quite often a test-fixture is needed which connects the ports of the device under test with the measurement equipment. The consequence is that the performance of the test-fixture is also included in the measurement results. In this webinar, different methods will be discussed to de-embed the test-fixture performance from the measurement results. More specifically, the differences between a standard 2x thru and an impedance corrected 2x thru technique will be highlighted.
May 28, 2020
Component XTLK Characterization by ICN
Watch Video | Download PPT
Presented by: Steve Krooswyk
Characterizing component crosstalk in the frequency domain alone can be difficult: judgement of the best between two similar curves can puzzle the most experienced designer, and their correlation to system performance may not always be clear. In this talk we propose crosstalk characterization for connectors and cables by integrated crosstalk noise, and support the discussion with simulation.
May 21, 2020
Quantifying Glass Induced Skew on PCBs
Watch Video | Download PPT
Presented by: Brandon Gore
So, for your ultra-high speed PCB design, you have chosen the best options available to you: a top end PCB material, a mechanically spread glass weave, layers with multiple ply and high resin content. How much skew can you expect? Are there other mitigation techniques? In this Samtec gEEk® spEEk webinar, we share results from our measurement based skew platform, and offer skew mitigation techniques we use on our signaling evaluation platforms. Brandon Gore, PhD, is a senior staff engineer at Samtec and currently manages the R&D team within the Signal Integrity Group. He also participates in OIF-CEI-112G and IEEE P802.3ck Standards development projects. He received his doctorate in Electrical Engineering from the University of South Carolina in 2018. Prior to 2016, he spent 11 years at Intel Corporation within the Enterprise Packaging and Interconnect group for high speed signal integrity where his primary responsibilities were Ethernet and Fabric applications from CPU, FPGA, and Chipsets.
May 7, 2020
Twinax Basics
Watch Video | Download PPT
Presented by: John Abbott
As data rates scale to 112 Gbps and beyond, twin-axial cabling is becoming a vital part of system architecture and design. This Samtec gEEk® spEEk Zoom Webinar explores the numerous twin-ax construction options and their signal integrity advantages and challenges.
April 30, 2020
PCI Express: Is 85 Ohms Really Needed?
Watch Video
Presented by: Steve Krooswyk
In designing for PCIe, we believe we need to adhere to 85 ohm throughout the interconnect. Where does the 85 ohm spec come from? Is it always required? In this Samtec gEEk® spEEk Zoom webinar, we discuss these questions for PCB, packages, connectors and cables and review the specification so you may design with confidence.
RF
November 16, 2023
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures
Watch Video | Download PPT
Presenters: Matt Burns & Kiana Montes
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures Integrated RF SoCs are revolutionizing system architectures. Traditional RF interconnects strain form factor, weight and financial budgets as RF channel counts increase. In this webinar, Samtec technical experts will detail novel solutions for routing high-frequency RF signals via array connectors. Additionally, recommended launch optimizations and PCB stack-ups will be presented.
August 17, 2023
Mechanical Consideration for Compression Mount RF Connectors
Watch Video | Download PPT
Speaker: Zak Speraw
Compression mount connectors have become popular to overcome solder variation when populating mmWave RF interconnects. While they successfully overcome solder variability, new considerations are introduced that could reduce the performance at high frequencies. This talk explores the potential impact of board compression and pin alignment, and how to overcome.
December 15, 2022
Impacts of Solder Reflow on High Bandwidth RF Connectors
Watch Video | Download PPT
Presented by: Michael Griesi
In a perfect world, soldering a high bandwidth precision RF connector to an optimized PCB launch should be straightforward. In reality, results can vary from perfectly acceptable results to severely degraded electrical performance or catastrophic failures. Identifying and addressing root causes can be challenging with hidden solder joints and finite trace lengths. In this gEEk® spEEk webinar, Mr. Griesi will detail the side effects of standard solder reflow processes on PCB-mounted RF connectors and offer techniques to control and predict unwanted solder flow. Additional tips and tricks for application-specific optimized correlation of simulated and measured data will also be presented.
October 20, 2022
Precision RF Connector PCB Launches for 224 Gbps Devices
Watch Video | Download PPT
Presented by: Sandeep Sankararaman
The signal-to-noise ratio (SNR) at the input of a device is a critical factor in determining its performance. As the bandwidth of devices approach 100 GHz, it becomes very hard to maintain adequate levels of SNR across the full bandwidth. Connector launches also become increasingly challenging. This gEEk® spEEk webinar aims to demystify the principles behind the design of millimeter wave RF launches. The impact of different design features on stripline launches will be examined and practical approaches to getting the maximum performance will be explained.
October 22, 2020
XTLK Mitigation in 12G-SDI Systems
Watch Video | Download PPT
Presented by: Travis Ellis
12G-SDI Serial Digital Interface systems are architected around 75 Ohm single ended signaling. The cable reach of these systems is often degraded by the cross talk inherent in the interconnects used in these systems. This presentation will discuss common architectures and simple design enhancements that can improve cross talk by one to two orders of magnitude. Thus, providing cable reach closer to the ideal reach of greater than 100 meters.
October 8, 2020
Waveguides and Cut-off Frequencies
Watch Video | Download PPT
Presented by: Kelly Garrison
An introduction to non-TEM problems in SI design, or how knowing a little bit about waveguide will help with high frequency design. Several case studies will show the ways that a designer can be caught unawares both in simulation and in hardware, and how resonances can occur in structures you didn’t think could resonate. We’ll also cover the reason why connectors and cables are forced to get smaller and smaller as frequency increases, and an argument for escaping from TEM and embracing waveguide. Kelly Garrison has been a Signal Integrity engineer for 2 years at Samtec, working on Precision RF connectors, Glasscore, and Waveguide. He brings another 10 years of experience from the RF Test and Measurement industry, where he specialized in passive microwave component design. If you so much as think about filters, baluns, or waveguide, he will send you a Zoom link so you can talk about it. Kelly graduated from Portland State University with degrees in Electrical Engineering, Physics, and strangely, a minor in Russian, and still lives in the Portland area. He spends his days off fixing things that his four sons have broken and dreaming about the day when they’ll help him fix things that he’s broken.
EMI
June 23, 2022
Dual Reverberation Cavities for IO Connector EMI Performance
Watch Video | Download PPT
Presented by: Gary Biddle
Techniques using mode tuned resonant cavities to establish known field levels has enabled the EMC community to construct international immunity and emission test standards. IEC 61000-4 details methodology for testing electronic equipment in large reverberation chambers [LRC] to certify and predict device EMI performance in the free space environment. A relatively new method, dual reverberation cavities [DRC], offers the unique advantage of determining the electromagnetic power transfer through a passive device under test [DUT]. DRC integrates immunity and emission mode tuned techniques to evaluate a DUT mounted in an adjoining bulkhead. Results of connector IO product can be expressed in terms of screening effectiveness [ScrEff]. The presentation shows supporting mode tuned techniques and hardware, along with connector IO test results to 40 GHz.
Crosstalk
August 18, 2022
Cascaded or End-to-End Models: What Do We Give Up?
Watch Video | Download PPT
Presented by: Robert Branson
To combat increased simulation times, it is common practice to divide the board and multi-pin connector models into separate simulations that are then cascaded. This practice introduces impedance and crosstalk inaccuracies between simulation and measurements. This presentation demonstrates the differences through correlated simulation/measurement models. Field plots are used to show the inaccuracy created by the artificial simulation boundary. Then we study efforts to devise mitigation strategies to decrease simulation time while avoiding simulation inaccuracy, though the best solution often comes to a monolithic simulation.
October 14, 2021
Advanced HD BOR & Crosstalk Mitigation Strategies
Watch Video | Download PPT
Presented by: Travis Ellis
Today’s high density connector arrays face significant challenges at the board attach region. Insertion loss and return loss impairments can be mitigated with careful design and simulation. More importantly especially with PAM4 signally are the crosstalk impairments from the associated via fields. Sympathetic resonators can allow crosstalk to skip across the entire filed with minimal attenuation. This presentation will highlight these issues and demonstrate how to improve the connector & board ecosystem to assure successful system designs.
July 15, 2021
Common Mode Conundrums
Watch Video | Download PPT
Presented by: Richard Mellitz
It has long been thought that common mode impairments may be easily controlled with common mode specifications. Differential simulation may indeed have some common mode included within the signal and noise transmission. The problem emerges between specification for separable interfaces such as cards, connectors, and chips. IEEE802.3 and OIF CEI standards often include a collection of common mode specifications measured at test points for these separations or interfaces. As 112 Gb/s PAM4 becomes more common place it is worth exploring common mode specifications and what they mean for performance. What matters more and what is not so important. Discussions include the nature of common mode, a historical perspective, procedures to compute the effects of CM, CM measurements, and practices to minimize the effect of common on differential signaling.
October 22, 2020
XTLK Mitigation in 12G-SDI Systems
Watch Video | Download PPT
Presented by: Travis Ellis
12G-SDI Serial Digital Interface systems are architected around 75 Ohm single ended signaling. The cable reach of these systems is often degraded by the cross talk inherent in the interconnects used in these systems. This presentation will discuss common architectures and simple design enhancements that can improve cross talk by one to two orders of magnitude. Thus, providing cable reach closer to the ideal reach of greater than 100 meters.
May 28, 2020
Component XTLK Characterization by ICN
Watch Video | Download PPT
Presented by: Steve Krooswyk
Characterizing component crosstalk in the frequency domain alone can be difficult: judgement of the best between two similar curves can puzzle the most experienced designer, and their correlation to system performance may not always be clear. In this talk we propose crosstalk characterization for connectors and cables by integrated crosstalk noise, and support the discussion with simulation.
PCI Express
April 15, 2021
Successful PCIe® 4.0 Interconnect Guidelines
Watch Video | Download PPT
Presented by: Steve Krooswyk
System developers utilizing PCI Express are experiencing an increasing pressure to improve interconnect with each data rate increase. To help achieve the maximum routing lengths optimizations for loss, reflection, and crosstalk are all under the microscope. Questions begin to surface – How much optimization is really necessary, or when should I run channel simulation? In this talk we review the ingredients for a successful interconnect and how they change at each speed bump. Practical topics include guidelines for length and loss, the penalty from trace separation and via stubs, connectors and cables, and interpretation of channel simulation results.
May 28, 2020
Component XTLK Characterization by ICN
Watch Video | Download PPT
Presented by: Steve Krooswyk
Characterizing component crosstalk in the frequency domain alone can be difficult: judgement of the best between two similar curves can puzzle the most experienced designer, and their correlation to system performance may not always be clear. In this talk we propose crosstalk characterization for connectors and cables by integrated crosstalk noise, and support the discussion with simulation.
April 30, 2020
PCI Express: Is 85 Ohms Really Needed?
Watch Video
Presented by: Steve Krooswyk
In designing for PCIe, we believe we need to adhere to 85 ohm throughout the interconnect. Where does the 85 ohm spec come from? Is it always required? In this Samtec gEEk® spEEk Zoom webinar, we discuss these questions for PCB, packages, connectors and cables and review the specification so you may design with confidence.
IEEE-COM
July 15, 2021
Common Mode Conundrums
Watch Video | Download PPT
Presented by: Richard Mellitz
It has long been thought that common mode impairments may be easily controlled with common mode specifications. Differential simulation may indeed have some common mode included within the signal and noise transmission. The problem emerges between specification for separable interfaces such as cards, connectors, and chips. IEEE802.3 and OIF CEI standards often include a collection of common mode specifications measured at test points for these separations or interfaces. As 112 Gb/s PAM4 becomes more common place it is worth exploring common mode specifications and what they mean for performance. What matters more and what is not so important. Discussions include the nature of common mode, a historical perspective, procedures to compute the effects of CM, CM measurements, and practices to minimize the effect of common on differential signaling.
March 18, 2021
Mechanics of Using the Public COM Code
Watch Video | Download PPT
Presented by: Richard Mellitz
Channel Operating Margin (COM) is an electrical figure of merit for a channel derived from a measurement of its scattering parameters and a table of configuration parameters. These parameters may be represented as a machine readable form in a spreadsheet. COM is normative for many IEEE and OIF specification for data rates over 25 Gb/s. COM is described in Annex 93A of IEEE Std 802.3™-2018. An example of a COM implementation is available as a Matlab® script. The subject of this presentation illustrates the operation of the COM script as well as exploration of features of the many parameters and control keywords. The example of using COM explores the required reference packages and then segues into examples and caveats for utilizing the COM script with user packages. Operation are depicted as example screen shots.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
September 10, 2020
Noise and Simulation Correlation
Watch Video | Download PPT
Presented by: Richard Mellitz
Opinions on correlation range from intuitive to scientific. The presentation opens with an introduction of statistical terms. A simple example is used to illustrate a key question, “What is the purpose of the correlation?” An example of 100 Gbs / PAM-4 signaling correlation segues into BER correlation. Methods using noise parameters in COM are then used to correlate measured BER and simulated BER.
July 30, 2020
Signal Power & Noise and SI
Watch Video | Download PPT
Presented by: Richard Mellitz
The purpose is to tie it together: signals, noise power, and performance. This is a primer on how signal integrity (SI) simulations work. The context is differential signaling with data rates greater than 25 Gb/s. Examples include 100 Gb/s NRZ signaling and relations to PAM. Reviews include SI assumptions such as linear time invariance (LTI), summing noise power, superposition, and statistical convolution. A variety of other impairments such as jitter, semiconductor noise, etc. will not be covered for simplicity.
July 2, 2020
IEEE Channel Operating Margin (COM)
Watch Video | Download PPT
Presented by: Brandon Gore
During the development of the Ethernet Std-802.3 for 25 Gbps NRZ signaling, a paradigm shift happened for interconnect characterization. Frequency domain masks were replaced with an open source simulation method that ties transmitter, receiver and channel together. In this webinar presentation, we explore why these new methods where introduced and take a deeper dive into the physical representation of the reference packages.
Interconnect
November 16, 2023
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures
Watch Video | Download PPT
Presenters: Matt Burns & Kiana Montes
Array Connectors for Multi-Channel Antennas-to-Bits System Architectures Integrated RF SoCs are revolutionizing system architectures. Traditional RF interconnects strain form factor, weight and financial budgets as RF channel counts increase. In this webinar, Samtec technical experts will detail novel solutions for routing high-frequency RF signals via array connectors. Additionally, recommended launch optimizations and PCB stack-ups will be presented.
July 20, 2023
Breakout Design: Cable Connectors
Watch Video | Download PPT
Presenter: Scott McMorrow
Continuing the discussion from last month, Scott McMorrow provides a preview of advanced design methodology that is under development at Samtec, specifically the Samtec breakout region (BOR) methodology will be used on an NVAC near package cable (NPC) connector. Advanced BOR design methodology condenses the “final inch” of a design into a manageable region, and it was developed to addresses the complexity of designing breakouts for connectors at high data rate. Come see what the state of the art looks like and bring your questions.
June 15, 2023
Breakout Design: Package and Traces
Watch Video | Download PPT
Presenter: Scott McMorrow
Scott McMorrow explains the technical challenges of breakout region (BOR) design for packages and traces, noting how they can dramatically affect the performance of a channel. He will walk through a specific example, providing guidance on the design of the package side of a near package cable (NPC) BOR that includes 1mm pitch balls on a 30-layer board for 112Gbps PAM4. Come join this technical discussion on “final inch” design and bring your questions.
August 18, 2022
Cascaded or End-to-End Models: What Do We Give Up?
Watch Video | Download PPT
Presented by: Robert Branson
To combat increased simulation times, it is common practice to divide the board and multi-pin connector models into separate simulations that are then cascaded. This practice introduces impedance and crosstalk inaccuracies between simulation and measurements. This presentation demonstrates the differences through correlated simulation/measurement models. Field plots are used to show the inaccuracy created by the artificial simulation boundary. Then we study efforts to devise mitigation strategies to decrease simulation time while avoiding simulation inaccuracy, though the best solution often comes to a monolithic simulation.
February 24, 2022
Single Ended Design Analysis in a Different World
Watch Video | Download PPT
Presented by: Chris Kocuba
Differential analysis can mask high speed design or solver issues. Analyzing single ended data can bring these issues to light and allow the designer to reclaim performance that would otherwise be lost. These issues can be found in but not limited to: connector design, BORs, trace routing, signal definition and from model solver settings.
October 14, 2021
Advanced HD BOR & Crosstalk Mitigation Strategies
Watch Video | Download PPT
Presented by: Travis Ellis
Today’s high density connector arrays face significant challenges at the board attach region. Insertion loss and return loss impairments can be mitigated with careful design and simulation. More importantly especially with PAM4 signally are the crosstalk impairments from the associated via fields. Sympathetic resonators can allow crosstalk to skip across the entire filed with minimal attenuation. This presentation will highlight these issues and demonstrate how to improve the connector & board ecosystem to assure successful system designs.
September 16, 2021
Development of 112 Gbps PAM4 Test Platforms
Watch Video | Download PPT
Presented by: Jean-Remy Bonnefoy
The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This talk will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.
July 15, 2021
Common Mode Conundrums
Watch Video | Download PPT
Presented by: Richard Mellitz
It has long been thought that common mode impairments may be easily controlled with common mode specifications. Differential simulation may indeed have some common mode included within the signal and noise transmission. The problem emerges between specification for separable interfaces such as cards, connectors, and chips. IEEE802.3 and OIF CEI standards often include a collection of common mode specifications measured at test points for these separations or interfaces. As 112 Gb/s PAM4 becomes more common place it is worth exploring common mode specifications and what they mean for performance. What matters more and what is not so important. Discussions include the nature of common mode, a historical perspective, procedures to compute the effects of CM, CM measurements, and practices to minimize the effect of common on differential signaling.
June 17, 2021
Advanced Test Fixture Design
Watch Video | Download PPT
Presented by: Travis Ellis
Engineering systems for 112G introduces complex interdependent design challenges. More now than ever system engineers are forced to utilize a closed loop design process. Where 3D full wave simulations are used to validate designs before fabrication. Once fabricated these designs and their channel models must be correlated to measured data. To have clear picture of the results test fixtures must be transparent. Achieving fixture transparency is possible with careful design practices along with a deep understanding of what it takes to create these fixtures.
February 18, 2021
Bending EM Simulation Tools
Watch Video | Download PPT
Presented by: Scott McMorrow
There is an art and science to utilizing an electromagnetic modeling tool to analyze and optimize designs and obtain reasonable answers consistently. Session attendees will learn how to “trick” a tool into providing the most accurate insight possible for a design. We’ll talk about setup, ports, boundary conditions and other tricks of the trade that help derive the best results from EM Tools. We’ll also discuss quick ways to obtain approximate answers that will help engineers maximize their efficiency.
November 19, 2020
Practical Uses of ERL in BOR Design
Watch Video | Download PPT
Presented by: Scott McMorrow
In ERL Part 1, Samtec Distinguished Engineer Rich Mellitz discussed the foundations of Effective Return Loss (ERL as a metric for full link analysis. In Part 2, Samtec Strategic Technologist Scott McMorrow will discuss a practical usage of ERL in the analysis and optimization of via and connector Breakout Regions (BOR). ERL will be used as a valuable tool in the rapid and unambiguous selection of the best design for a given data rate out of multiple design iterations.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
September 24, 2020
Periodic Discontinuities
Watch Video | Download PPT
Presented by: Gustavo Blando
In this introductory talk, I’ll start by reviewing resonances commonly found in SI topologies in an intuitive way. In particular, I’ll concentrate on half wave resonances. At a very fundamental level I’ll discuss: What resonances are? How do they develop? And how to identify them with dips/peaks in the frequency domain S-parameters? The study of half wave resonances will set the baseline to understand periodical discontinuities. The theory will be presented first and then, several examples and practical mitigation strategies will be shown for both half wave resonances and periodical discontinuities.
August 13, 2020
Trace Corner Bends: OK or Not?
Watch Video | Download PPT
Presented by: Scott McMorrow
As system data rates become progressively faster, the difficulty of designing high-margin becomes more difficult each year. There are many misconceptions about the signal integrity implications of corner bends in high performance PCB designs. In this webinar, we will perform 3D electromagnetic investigations of individual and serpentine, single-ended and differential corners, to determine layout requirements for multiple data rate regimes. Clear guidance will be provided for both production and precision measurement board designs.
June 25, 2020
Trace Design for Crosstalk Reduction
Watch Video | Download PPT
Presented by: Scott McMorrow
Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined, and simple rules are derived that can be used to quickly aid in system design. Scott McMorrow currently serves as CTO for Samtec’s Signal Integrity Group, Inc. As a consultant for years too numerous to mention, Scott has helped many companies develop high performance products, while training signal integrity engineers. Today he works for “the man,” where he continues being a problem solver, a change agent and “betting his job” every day.
June 18, 2020
Breakout Region Design by Inspection
Watch Video | Download PPT
Presented by: Travis Ellis
What can you do to check your layout and design breakouts with your eyes. Travis Ellis is a signal integrity practitioner working with customers to successfully deliver their systems to market. He believes signal integrity is critical for success and has delivered many innovative solutions across multiple industries. Travis holds a mechanical engineering degree from Portland State University. Travis enjoys the outdoors and the opportunity to work with many talented peers.
Mechanical / Manufacturing
September 16, 2021
Development of 112 Gbps PAM4 Test Platforms
Watch Video | Download PPT
Presented by: Jean-Remy Bonnefoy
The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This talk will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.
May 21, 2020
Quantifying Glass Induced Skew on PCBs
Watch Video | Download PPT
Presented by: Brandon Gore
So, for your ultra-high speed PCB design, you have chosen the best options available to you: a top end PCB material, a mechanically spread glass weave, layers with multiple ply and high resin content. How much skew can you expect? Are there other mitigation techniques? In this Samtec gEEk® spEEk webinar, we share results from our measurement based skew platform, and offer skew mitigation techniques we use on our signaling evaluation platforms. Brandon Gore, PhD, is a senior staff engineer at Samtec and currently manages the R&D team within the Signal Integrity Group. He also participates in OIF-CEI-112G and IEEE P802.3ck Standards development projects. He received his doctorate in Electrical Engineering from the University of South Carolina in 2018. Prior to 2016, he spent 11 years at Intel Corporation within the Enterprise Packaging and Interconnect group for high speed signal integrity where his primary responsibilities were Ethernet and Fabric applications from CPU, FPGA, and Chipsets.
Test Platforms
April 28, 2022
Mitigating the Effects of Connector Mating/Normal Forces in SI
Watch Video | Download PPT
Presented by: Juan Aguirre
Normal forces are a critical specification in the mating of high-performance interconnects. Normal forces minimize or eliminate oxide build-up, affect contact pin deflection, and determine surface contact area. Changes in normal forces can be observed in standard SI parameters including characteristic impedance, TDR ad RL. In this course, technical experts from Samtec will discuss measurement techniques for spotting normal force discontinuities. Mitigation solutions will also be presented.
June 17, 2021
Advanced Test Fixture Design
Watch Video | Download PPT
Presented by: Travis Ellis
Engineering systems for 112G introduces complex interdependent design challenges. More now than ever system engineers are forced to utilize a closed loop design process. Where 3D full wave simulations are used to validate designs before fabrication. Once fabricated these designs and their channel models must be correlated to measured data. To have clear picture of the results test fixtures must be transparent. Achieving fixture transparency is possible with careful design practices along with a deep understanding of what it takes to create these fixtures.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
Measurement
Februrary 15, 2024
Deep Dive into PCB Characteristics for Correlation/Simulation at 224G and Below
Watch Video | Download PPT
Presented by: Robert Branson, Greylan Smoak, Scott McMorrow & Steve Krooswyk
This discussion will look at techniques for simulating high-accuracy PCB structures to achieve accurate correlation for 224G performance. This topic is based on the work from our DesignCon paper, and will likewise look at modeling techniques that do not require the building of a test coupon.
June 23, 2022
Dual Reverberation Cavities for IO Connector EMI Performance
Watch Video | Download PPT
Presented by: Gary Biddle
Techniques using mode tuned resonant cavities to establish known field levels has enabled the EMC community to construct international immunity and emission test standards. IEC 61000-4 details methodology for testing electronic equipment in large reverberation chambers [LRC] to certify and predict device EMI performance in the free space environment. A relatively new method, dual reverberation cavities [DRC], offers the unique advantage of determining the electromagnetic power transfer through a passive device under test [DUT]. DRC integrates immunity and emission mode tuned techniques to evaluate a DUT mounted in an adjoining bulkhead. Results of connector IO product can be expressed in terms of screening effectiveness [ScrEff]. The presentation shows supporting mode tuned techniques and hardware, along with connector IO test results to 40 GHz.
September 16, 2021
Development of 112 Gbps PAM4 Test Platforms
Watch Video | Download PPT
Presented by: Jean-Remy Bonnefoy
The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This talk will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.
June 17, 2021
Advanced Test Fixture Design
Watch Video | Download PPT
Presented by: Travis Ellis
Engineering systems for 112G introduces complex interdependent design challenges. More now than ever system engineers are forced to utilize a closed loop design process. Where 3D full wave simulations are used to validate designs before fabrication. Once fabricated these designs and their channel models must be correlated to measured data. To have clear picture of the results test fixtures must be transparent. Achieving fixture transparency is possible with careful design practices along with a deep understanding of what it takes to create these fixtures.
May 20, 2021
Causality Enforcement
Watch Video | Download PPT
Presented by: Stefaan Sercu
The quality of time domain simulation results, using Fourier transformations (e.g. COM simulations), depends highly on the quality of the S–parameter models used. Causality is shown to be an important parameter limiting the usefulness of a model. In this webinar we show that causality problems can be classified as mathematical and physical in origin.
January 21, 2021
S & Z Parameters for PDN
Watch Video | Download PPT
Presented by: Istvan Novak
In signal integrity, describing passive devices and channels with S parameters has become the norm. Power distribution is different. Dependent on the application, other forms may be best for the purpose. First we will focus on the scattering parameters of bypass capacitors. We will explain with measured and simulated data, how to use the Touchstone models that are created for series or parallel connected capacitors. Next, we will learn why design is usually done with impedances, while measurements are still done with S parameters.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
June 11, 2020
Impedance Corrected De-Embedding
Watch Video | Download PPT
Presented by: Stefaan Sercu
To perform accurate measurements of devices, quite often a test-fixture is needed which connects the ports of the device under test with the measurement equipment. The consequence is that the performance of the test-fixture is also included in the measurement results. In this webinar, different methods will be discussed to de-embed the test-fixture performance from the measurement results. More specifically, the differences between a standard 2x thru and an impedance corrected 2x thru technique will be highlighted.
May 21, 2020
Quantifying Glass Induced Skew on PCBs
Watch Video | Download PPT
Presented by: Brandon Gore
So, for your ultra-high speed PCB design, you have chosen the best options available to you: a top end PCB material, a mechanically spread glass weave, layers with multiple ply and high resin content. How much skew can you expect? Are there other mitigation techniques? In this Samtec gEEk® spEEk webinar, we share results from our measurement based skew platform, and offer skew mitigation techniques we use on our signaling evaluation platforms. Brandon Gore, PhD, is a senior staff engineer at Samtec and currently manages the R&D team within the Signal Integrity Group. He also participates in OIF-CEI-112G and IEEE P802.3ck Standards development projects. He received his doctorate in Electrical Engineering from the University of South Carolina in 2018. Prior to 2016, he spent 11 years at Intel Corporation within the Enterprise Packaging and Interconnect group for high speed signal integrity where his primary responsibilities were Ethernet and Fabric applications from CPU, FPGA, and Chipsets.
May 7, 2020
Twinax Basics
Watch Video | Download PPT
Presented by: John Abbott
As data rates scale to 112 Gbps and beyond, twin-axial cabling is becoming a vital part of system architecture and design. This Samtec gEEk® spEEk Zoom Webinar explores the numerous twin-ax construction options and their signal integrity advantages and challenges.
Modeling
Februrary 15, 2024
Deep Dive into PCB Characteristics for Correlation/Simulation at 224G and Below
Watch Video | Download PPT
Presented by: Robert Branson, Greylan Smoak, Scott McMorrow & Steve Krooswyk
This discussion will look at techniques for simulating high-accuracy PCB structures to achieve accurate correlation for 224G performance. This topic is based on the work from our DesignCon paper, and will likewise look at modeling techniques that do not require the building of a test coupon.
September 21, 2023
How to Bring S-Parameters into Your Simulation Tool
Watch Video | Download PPT
Presented by: Tedd Wang
Using interconnect simulations as part of your system design allows you to see the effects of mechanical characteristics on electrical performance. But which tool should you use? And, once you have selected a toolset, what is the best way to tune your model into your channel. Join modeling experts from Samtec’s Signal Integrity Group as they address frequently asked questions and talk through common modeling sticking points, by showing detailed examples of how to quickly use the S-parameter model for the connector and the channel evaluation in ADS tool.
February 18, 2021
Bending EM Simulation Tools
Watch Video | Download PPT
Presented by: Scott McMorrow
There is an art and science to utilizing an electromagnetic modeling tool to analyze and optimize designs and obtain reasonable answers consistently. Session attendees will learn how to “trick” a tool into providing the most accurate insight possible for a design. We’ll talk about setup, ports, boundary conditions and other tricks of the trade that help derive the best results from EM Tools. We’ll also discuss quick ways to obtain approximate answers that will help engineers maximize their efficiency.
November 5, 2020
What is ERL? How is it Computed?
Watch Video | Download PPT
Presented by: Richard Mellitz
Equalization is essential for optimizing channel performance. How can SI engineers account for it? Enter effective return loss (ERL). First introduced in IEEE 802.3cd by Samtec distinguished Engineer Rich Mellitz, ERL provides a figure of merit for signal channels in equalized systems. However, what really is ERL? How can SI engineers leverage this metric? Please join Rich Mellitz as he answers these and related questions in Samtec’s next episode of gEEk spEEk.
October 8, 2020
Waveguides and Cut-off Frequencies
Watch Video | Download PPT
Presented by: Kelly Garrison
An introduction to non-TEM problems in SI design, or how knowing a little bit about waveguide will help with high frequency design. Several case studies will show the ways that a designer can be caught unawares both in simulation and in hardware, and how resonances can occur in structures you didn’t think could resonate. We’ll also cover the reason why connectors and cables are forced to get smaller and smaller as frequency increases, and an argument for escaping from TEM and embracing waveguide. Kelly Garrison has been a Signal Integrity engineer for 2 years at Samtec, working on Precision RF connectors, Glasscore, and Waveguide. He brings another 10 years of experience from the RF Test and Measurement industry, where he specialized in passive microwave component design. If you so much as think about filters, baluns, or waveguide, he will send you a Zoom link so you can talk about it. Kelly graduated from Portland State University with degrees in Electrical Engineering, Physics, and strangely, a minor in Russian, and still lives in the Portland area. He spends his days off fixing things that his four sons have broken and dreaming about the day when they’ll help him fix things that he’s broken.
September 24, 2020
Periodic Discontinuities
Watch Video | Download PPT
Presented by: Gustavo Blando
In this introductory talk, I’ll start by reviewing resonances commonly found in SI topologies in an intuitive way. In particular, I’ll concentrate on half wave resonances. At a very fundamental level I’ll discuss: What resonances are? How do they develop? And how to identify them with dips/peaks in the frequency domain S-parameters? The study of half wave resonances will set the baseline to understand periodical discontinuities. The theory will be presented first and then, several examples and practical mitigation strategies will be shown for both half wave resonances and periodical discontinuities.
August 13, 2020
Trace Corner Bends: OK or Not?
Watch Video | Download PPT
Presented by: Scott McMorrow
As system data rates become progressively faster, the difficulty of designing high-margin becomes more difficult each year. There are many misconceptions about the signal integrity implications of corner bends in high performance PCB designs. In this webinar, we will perform 3D electromagnetic investigations of individual and serpentine, single-ended and differential corners, to determine layout requirements for multiple data rate regimes. Clear guidance will be provided for both production and precision measurement board designs.
June 25, 2020
Trace Design for Crosstalk Reduction
Watch Video | Download PPT
Presented by: Scott McMorrow
Returning to basics, we’ll investigate the relationship of trace geometry to crosstalk in interconnect design, and draw some conclusions based on system constraints. Microstrip, stripline, and dual-stripline layer geometries will be examined, and simple rules are derived that can be used to quickly aid in system design. Scott McMorrow currently serves as CTO for Samtec’s Signal Integrity Group, Inc. As a consultant for years too numerous to mention, Scott has helped many companies develop high performance products, while training signal integrity engineers. Today he works for “the man,” where he continues being a problem solver, a change agent and “betting his job” every day.
June 18, 2020
Breakout Region Design by Inspection
Watch Video | Download PPT
Presented by: Travis Ellis
What can you do to check your layout and design breakouts with your eyes. Travis Ellis is a signal integrity practitioner working with customers to successfully deliver their systems to market. He believes signal integrity is critical for success and has delivered many innovative solutions across multiple industries. Travis holds a mechanical engineering degree from Portland State University. Travis enjoys the outdoors and the opportunity to work with many talented peers.
June 11, 2020
Impedance Corrected De-Embedding
Watch Video | Download PPT
Presented by: Stefaan Sercu
To perform accurate measurements of devices, quite often a test-fixture is needed which connects the ports of the device under test with the measurement equipment. The consequence is that the performance of the test-fixture is also included in the measurement results. In this webinar, different methods will be discussed to de-embed the test-fixture performance from the measurement results. More specifically, the differences between a standard 2x thru and an impedance corrected 2x thru technique will be highlighted.
May 21, 2020
Quantifying Glass Induced Skew on PCBs
Watch Video | Download PPT
Presented by: Brandon Gore
So, for your ultra-high speed PCB design, you have chosen the best options available to you: a top end PCB material, a mechanically spread glass weave, layers with multiple ply and high resin content. How much skew can you expect? Are there other mitigation techniques? In this Samtec gEEk® spEEk webinar, we share results from our measurement based skew platform, and offer skew mitigation techniques we use on our signaling evaluation platforms. Brandon Gore, PhD, is a senior staff engineer at Samtec and currently manages the R&D team within the Signal Integrity Group. He also participates in OIF-CEI-112G and IEEE P802.3ck Standards development projects. He received his doctorate in Electrical Engineering from the University of South Carolina in 2018. Prior to 2016, he spent 11 years at Intel Corporation within the Enterprise Packaging and Interconnect group for high speed signal integrity where his primary responsibilities were Ethernet and Fabric applications from CPU, FPGA, and Chipsets.
May 7, 2020
Twinax Basics
Watch Video | Download PPT
Presented by: John Abbott
As data rates scale to 112 Gbps and beyond, twin-axial cabling is becoming a vital part of system architecture and design. This Samtec gEEk® spEEk Zoom Webinar explores the numerous twin-ax construction options and their signal integrity advantages and challenges.
For More Information
Please contact us at [email protected] with any additional questions. Stay tuned to the Samtec blog for more details on future gEEk® spEEk events.