gEEk spEEk – Key Development Steps of 112 Gbps PAM4 Test Platforms

Presented by: Jean-Remy Bonnefoy The continued progression to higher data rates puts increasing demands on the design of practical SerDes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This talk will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.