gEEk spEEk – Successful PCIe Interconnect Guidelines for 8, 16, and 32 GT/s

Presented by: Steve Krooswyk System developers utilizing PCI Express are experiencing an increasing pressure to improve interconnect with each data rate increase. To help achieve the maximum routing lengths optimizations for loss, reflection, and crosstalk are all under the microscope. Questions begin to surface – How much optimization is really necessary, or when should I run channel simulation? In this talk we review the ingredients for a successful interconnect and how they change at each speed bump. Practical topics include guidelines for length and loss, the penalty from trace separation and via stubs, connectors and cables, and interpretation of channel simulation results.